1. Field of the Invention
This invention relates to a semiconductor integrated circuit device having a complementary type internal logic function element and to be used for a master slice type gate array LSI. More particularly, the present invention is concerned with a semiconductor integrated circuit device having two transmission gates.
2. Discussion of Background
Generally, in a MOS (metal oxide semiconductor) circuit, transmission gates are often used as the switching circuit.
FIG. 1 of the accompanying drawing is a transistor circuit diagram where the transmission gates are realized by a complementary MOS circuit (this circuit will hereinafter be abbreviated as "CMOS"). In the drawing, reference numerals 1 and 2 designate respectively a p-channel type MOS transistor and an n-channel type MOS transistor; numerals 3 and 4 refer to an input terminal and an output terminal, respectively; and reference letters C and C designate gate inputs for the p-channel type MOS transistor 1 and the n-channel type MOS transistor 2, respectively, having mutually inverted signals.
The transmission gate of the above-described construction operates in the following manner: in a state where the signal C is maintained at a ground potential and the signal C is maintained at a VDD potential, both p-channel type MOS transistor 1 and the n-channel type MOS transistor 2 assume an "off" condition and a region between the source and the drain is electrically shut off, while, in a state where the signal C is maintained at a VDD potential and the signal C is maintained at a ground potential, both p-channel type MOS transistor 1 and n-channel type MOS transistor 2 assume an "on" condition and a region between the source and the drain is electrically connected, whereby the transmission gate is in a conductive state.
As one example of using this transmission gate, there is a D-latch as shown in FIG. 2 of the acompanying drawing. In the drawing, reference numerals I and II designate respectively the transmission gates as shown in FIG. 1 above, which are constructed with the MOS transistors 1 and 2. The transmission gate I is to the input side, while the transmission gate II is to the feeback side. III and IV are respectively an input side inverter and a feedback side inverter, each being realized by the CMOS circuit constructed with a pair of the p-channel type MOS transistor 5a and the n-channel type MOS transistor 5b; numerals 6 and 7 are respectively a positive electrode (VDD) terminal and a negative electrode (GND) terminal; and T and T are respectively clock inputs having mutually inverted signals. D and Q designate respectively an input signal terminal and an output signal terminal.
In the D-latch of the above-described construction, the two transmission gates I and II operate in mutually opposite modes, i.e., when the one is in a conductive state, the other is always shut off, so that there is no possibility of both gates being in a conductive state or in a shut-off state simultaneously. If it is now assumed that the clock input T is maintained at the VDD potential, and the clock input T at the GND potential, the transmission gate I at the input side becomes conductive, a value of the input signal D is taken thereinto, and a signal corresponding to the input signal D appears at the output terminal Q through the input side of inverter III. Next, when the clock input T changes to the VDD potential, while the clock input T to the GND potential, the transmission gate II at the feedback side becomes conductive and maintains the output Q at a value corresponding to the value of the input D immediately before the clock inputs T and T change by means of the inverter IV and through the inverter III.
In the following, explanations will be made of a manner, in which the D-latch of the abovementioned circuit construction has so far been formed on a substrate. First of all, a master chip of a condition, in which the working steps common to those in the manufacturing steps of the master slice type LSI have been completed (a condition wherein no aluminum wiring has yet been applied) as shown in FIG. 3 of the accompanying drawing, is fabricated. In FIG. 3, a reference numeral 101 designates a region formed on a p-type semiconductor substrate 100 (to be also the substrate for the n-channel type MOS transistor), in which an n-type impurity has been diffused and which is to be the substrate for the p-channel type MOS transistor. Numerals 201 to 211 refer to p.sup.+ diffusion regions formed in this n-well region 101, which are the active regions to be the source or drain region for the p-channel type MOS transistor. 301 to 311 represent n.sup.+ diffusion regions formed in the abovementioned p-type semiconductor substrate 100, which are the active regions to be the source or drain for the n-channel type MOS transistor and arranged in correspondence to the abovementioned p.sup.+ diffusion regions 201 to 211 respectively. Numerals 401 to 410 refer to gates for the p-channel type MOS transistor made of poly-crystalline silicon and which are formed between the adjacent p.sup.+ diffusion regions 201 to 211 through an insulating film. Reference numerals 501 to 510 represent gates for the n-channel type MOS transistor made of poly-crystalline silicon and which are formed between the adjacent n.sup.+ diffusion regions 301 to 311 through an insulating film and are disposed in correspondence to the abovementioned gates 401 to 410 for the p-channel type MOS transistors, respectively.
Then, on this master chip as shown in FIGS. 3 wherein the basic transistor pair consisting of a pair of the p-channel type MOS transistor and the n-channel type MOS transistor are arranged in the form of an array, there is formed the first aluminum layer having a predetermined pattern through an inter-layer insulating film, and further formed thereover the second aluminum layer having a predetermined pattern through an inter-layer insulating film. From this structure, a construction as shown in FIG. 4 is obtained by effecting electrical connection through a window opened in the inter-layer insulating film between the master chip and the first aluminum layer (this window will hereinafter be called "contact hole") and a window opened in the inter-layer insulating film between the first aluminum layer and the second aluminum layer (this window will hereinfater be called "through-hole") so as to make the circuit construction as shown in FIG. 2.
Incidentally, in FIG. 4, the transmission gate 1 at the input side is constructed with a portion held between A--A' and B--B', i.e., the p-channel type MOS transistor 1 having the gate 406 and the p.sup.+ diffusion regions 206, 207, and the n-channel type MOS transistor 2 having the gate 505 and the n.sup.+ diffusion regions 305, 306; the transmission gate II at the feedback side is constructed with a portion held between A--A' and C--C', i.e., the p-channel type MOS transistor 1 having the gate 402 and the p.sup.+ diffusion regions 202, 203, and the n-channel type MOS transistor 2 having the gate 503 and the n.sup.+ diffusion regions 303, 304; the inverter III at the input side is constructed with a portion held between B--B' and D--D', i.e., the gate 408 and the p-channel type MOS transistor 5a having the p.sup.+ diffusion regions 208, 209 and the n-channel type MOS transistor 5b having the n.sup.+ diffusion regions 308, 309; and the inverter IV at the feedback side is constructed with a portion held between D--D' and E--E', i.e., the p-channel type MOS transistor 5a having the gate 409 and the p.sup.+ diffusion regions 209, 210 and the n-channel type MOS transistor 5b having the gate 509 and the n.sup.+ diffusion regions 309, 310.
More detailed explanations will be given in the following as to the structure of the D-latch shown in FIG. 4 in further reference to FIGS. 5 and 6. In the drawing, a reference numeral 601 designates a field insulating film formed on the substrate; 602 refers to an inter-layer insulating film formed on the p.sup.+ diffusion regions 201 to 211, n.sup.+ diffusion regions 301 to 311, the gates 401 to 410, 501 to 510, and the field insulating film 601; and 701 to 711 represent the first aluminum layers (those portions shaded with hatch lines as in FIG. 4) which are formed on the basis of a predetermined pattern formed on this inter-layer insulating film 602. Here, the first aluminum layers 701, 702 respectively serve as the VDD lines for supplying a VDD potential and a GND line for supplying a GND potential, wherein the gates 401, 404, 407 and 410 are connected with the VDD line 701 through the contact hole 901 and the gates 501, 504, 507, and 510 are connected with the GND line 702 also through the contact hole 901 to electrically separate the adjacent logic function elements. At the same time, the p.sup.+ diffusion region 209 (to be the source region) to construct the p-channel type MOS transistor 5a of the inverters III and IV is connected with the VDD line 701 through the contact hole 901 to which the VDD potential is supplied, while the n.sup.+ diffusion regions 309 (to be the source region) for constructing the n-channel type MOS transistor 5b of the inverters III and IV is connected with the GND line 702 through the contact hole 901, to which the GND potential is supplied. The first aluminum layers 703, 704 constitute input lines to be connected respectively with the p.sup.+ diffusion region 207 (to be the source region) for constructing the p-channel type MOS transistor 1 of the transmission gate I at the input side through the contact hole 901, and with the n.sup.+ diffusion region 305 (to be the source region) for constructing the n-channel type MOS transistor of the transmission gate I at the input side also through the contact hole 901. The first aluminum layer 705 constitutes an output line to be connected with the p.sup.+ diffusion region 208 (to be the drain region) for constructing the p-channel type MOS transistor 5a of the inverter III at the input side and the n.sup.+ diffusion region 308 (to be the drain region) for constructing the n-channel type MOS transistor 5b, and with the gate 409 for constructing the p-channel type MOS transistor 5a and the gate 509 for constructing the n-channel type MOS transistor 5b of the inverter IV at the feedback side through the respective contact holes 901. The first aluminum layer 706, 707 are clock lines to connect the gate 406 for constructing the p-channel type MOS transistor 1 of the transmission gate I at the input side with the gate 506 corresponding thereto through the contact hole 901 as well as the gate 505 for constructing the n-channel type MOS transistor 2 of the transmission gate I at the input side with the gate 405 corresponding thereto also through the contact hole 901. The first aluminum layers 708, 709 are also the clock lines which connect the gate 402 for constructing the p-channel type MOS transistor 1 of the transmission gate II at the feedback side with the gate 502 corresponding thereto through the contact hole 901 as well as the gate 503 for constructing the n-channel type MOS transistor 2 of the transmission gate II at the feedback side with the gate 403 also through the contact hole 901. The first aluminum layer 710 is a line for wiring, which connects the p.sup.+ diffusion region 206 (to be the drain region) for constructing the p-channel type MOS transistor 1 of the transmission gate I at the input side with the n.sup.+ diffusion region 306 (to be the drain region) for constructing the n-channel type MOS transistor 2 of the same, the p.sup.+ diffusion region 203 (to be the drain region) for constructing the p-channel type MOS transistor 1 of the transmission gate II at the feedback side wtih the n.sup.+ diffusion region 303 constructing the n-channel type MOS transistor 2 of the same, and the gate 408 for constructing the p-channel type MOS transistor 5a of the inverter III at the input side with the gate 508 for constructing the n-channel type MOS transistor 5b of the same, through their respective contact holes 901. The first aluminum layer 711 is a line for wiring, which connects the p.sup.+ diffusion region 202 (to be the source region) for constructing the p-channel type MOS transistor 1 of the transmission gate II at the feedback side with the n.sup.+ diffusion region 304 (to be the source region) for constructing the n-channel type MOS transistor 2 of the same, and the p.sup.+ diffusion region 210 (to be the drain region) for constructing the p-channel type MOS transistor 5a of the inverter IV at the feedback side with the n.sup.+ diffusion region 310 (to be the drain region) for constructing the n-channel type MOS transistor 5b of the same, through the respective contact holes 901. A numeral 603 designates an inter-layer insulating film formed on these first aluminum layers 701 to 711 and the inter-layer insulating film 602, and numerals 801 to 806 refer to the second aluminum layers (portions in FIG. 4 where shaded with hatch lines in criss-cross form) which are formed on the basis of a predetermined pattern formed on this inter-layer insulating film 603. Here, the second aluminum layer 801 denotes a D-input signal line which is connected with the first aluminum layers 703, 704 through the through-holes 902. The second aluminum layers 802, 803 constitute T-input signal lines which are connected with the first aluminum layers 707, 708, respectively, through the through-holes 902. The second aluminum layers 804, 805 constitute T input signal lines which are connected with the first aluminum layers 706, 709, respectively, through the through-holes 902. The second aluminum layer 806 constitutes a Q-output signal line and is connected with the first aluminum layer 705 through the through-holes 902. A numeral 604 refers to a protective film for protecting the surface of the semiconductor. Incidentally, the n-well region 101 is always fixed at the VDD potential or a potential higher than the VDD potential, while the p-type semiconductor substrate 100 is always fixed at the GND potential or a potential lower than the GND potential.
In such construction, however, as will be apparent from FIG. 4, there are formed the p.sup.+ diffusion regions 204, 205 and the n.sup.+ diffusion regions 302, 307 which are not used in constructing the circuit in the two transmission gates I and II which operate in the mutually opposite modes with the consequent problem in increasing the degree of integration.